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Authors: Van-Diep Duong
Issue Date: 2013
Abstract: It is easy to realize that a product can not be sent to customers without an efficient testing process. Testing plays an important role in production cycle and the cost of test is about 40% of the cost of building a product. Nowadays, the rapid development of digital integrated circuits, the decrease of feature size and bonding techniques create a number of challenges when testing. Testability therefore becomes one of the major concerns for designers. Normally, testing is only performed at the end of the production cycle , but that brings many issues to testing process. Hence, testing should be an important part of design flow. Design-for-Test/Testability (DfT) techniques that improve the controllability and observability of the design can solve there issues. The purpose of this thesis is to investigate and design a DfT architecture based on boundary scan technique which is widely used in the industry. The designed DfT is aimed to be applied for testing embedded cores in systems on chip. In our case, to validate the implemented hardware architecture, we apply this architecture to a Delta-Sigma algorithm based motion detection IP core which is developed at the Key Laboratory for Smart Integrated Systems (SIS Lab) of VNU University of Engineering and Technology (VNU-UET). With the test patterns generated by TetraMAX ATPG tool of Synopsys for stuck-at fault model, the applied DfT architecture provides 100% fault coverage in testing the targeted motion detection IP core.
Appears in Collections:Khóa luận Khoa Vật lý kỹ thuật và Công nghệ Nano

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