Please use this identifier to cite or link to this item: https://lib.uet.vnu.edu.vn/jspui/handle/123456789/2131
Title: Hardware Debug Architecture for a SAP 8-bit Microprocessor
Authors: Thi-Huong Ta
Issue Date: 2013
Abstract: Nowadays, the integrated circuits (ICs) become much more complex than to the rapid evolution of semi conduction technology. Almost ICs include from one to plural processors to meet the increasingly demand of applications. There processors need to be verified and debugged for error, even on silicon, to be sure that they operate correctly before being embedded into application devices. This will help us to reduce product cost. Using a process called silicon debug, we can try to determine the location of errors in microprocessor. The process of debuging a microprocessor is very complex, include hardware and software debug tools. Hardware breakpoint can support to break at any time, it performs access I/O port. Moreover, it can stop at the executed processing in memory; for this reason, I use hardware debug method in my thesis. JTAG standard to hardware debug microprocessor is one of the most effect ways. To solve the problem, I will use the boundary scan register in JTAG standard to give control signal into the microprocessor then read the data out of microprocessor to support the debugging. The arm of thesis is use TAP controller of JTAG standard to apply on Simple-As-Possible (SAP) computer and give correct result. By analysis the architecture of SAP, I prevent some points to break system and read out data. This thesis has completed simulation and gets data out in correct breakpoint.
URI: https://lib.uet.vnu.edu.vn/jspui/handle/123456789/2131
Appears in Collections:Khóa luận Khoa Vật lý kỹ thuật và Công nghệ Nano

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